This invention relates to the field of integrated circuits; and, more particularly, to integrated circuits including capacitors.
Integrated circuits (ICs) may incorporate capacitors above the top level of interconnect metal. Passivating the electrodes and making contact to the electrodes while minimizing IC fabrication cost and complexity presents a challenge. A common connection scheme is to use bond pad metallization to contact the top of the capacitor. The capacitor is e.g., at a higher level than the top interconnect metal, thus presenting the bond pad via etch process with more than one target depth. Adding a photolithographic cycle to separately form capacitor interconnect vias increases IC fabrication costs and offsets the advantage of incorporating the capacitor on the IC.